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RTL8139D Datasheet PDF : 67 Pages
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RTL8139DL
Datasheet
5.2. Transmit Status Register
(TSD0-3)(Offset 0010h-001Fh, R/W)
The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8139D(L)
when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written. It is not affected
when software writes to these bits. These registers are only permitted to write by double-word access. After
software reset, all bits except OWN bit are reset to “0”.
Bit
31
30
29
28
27-24
23-22
21-16
15
14
13
12-0
R/W
R
R
R
R
R
-
R/W
R
R
R/W
R/W
Symbol
CRS
TABT
OWC
CDH
NCC3-0
-
ERTXTH5-0
TOK
TUN
OWN
SIZE
Description
Carrier Sense Lost: This bit is set to 1 when the carrier is lost during
transmission of a packet.
Transmit Abort: This bit is set to 1 if the transmission of a packet was
aborted. This bit is read only, writing to this bit is not affected.
Out of Window Collision: This bit is set to 1 if the RTL8139D(L)
encountered an "out of window" collision during the transmission of a
packet.
CD Heart Beat: The NIC watches for a collision signal (ie, CD
Heartbeat signal) during the first 6.4us of the interframe gap following a
transmission. This bit is set if the transceiver fails to send this signal.
This bit is cleared in the 100 Mbps mode.
Number of Collision Count: Indicates the number of collisions
encountered during the transmission of a packet.
Reserved
Early Tx Threshold: Specifies the threshold level in the Tx FIFO to
begin the transmission. When the byte count of the data in the Tx FIFO
reaches this level, (or the FIFO contains at least one complete packet)
the RTL8139D(L) will transmit this packet.
000000 = 8 bytes
These fields count from 000001 to 111111 in unit of 32 bytes.
This threshold must avoid exceeding 2K bytes.
Transmit OK: Set to 1 indicates that the transmission of a packet was
completed successfully and no transmit underrun has occurred.
Transmit FIFO Underrun: Set to 1 if the Tx FIFO was exhausted
during the transmission of a packet. The RTL8139D(L) can re-transfer
data if the Tx FIFO underruns and can also transmit the packet to the
wire successfully even though the Tx FIFO underruns. That is, when
TSD<TUN>=1, TSD<TOK>=0 and ISR<TOK>=1 (or ISR<TER>=1).
OWN: The RTL8139D(L) sets this bit to 1 when the Tx DMA
operation of this descriptor was completed. The driver must set this bit
to 0 when the Transmit Byte Count (bits 0-12) is written. The default
value is 1.
Descriptor Size: The total size in bytes of the data in this descriptor. If
the packet length is more than 1792 byte (0700h), the Tx queue will be
invalid, i.e. the next descriptor will be written only after the OWN bit of
that long packet's descriptor has been set.
Single Chip Multifunction 10/100 Ethernet Controller w/Power Management 11 Track ID: JATR-1076-21 Rev. 1.2

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