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MX98728EC

GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION

Macronix International 

MX98728EC

Network Control Register B : NCRB (Reg1h),R/W, default=01h

Bit

1.0

1.1

1.2

1.3

1.4

1.5

1.7-6

Symbol

Description

PR*

Promiscuous mode: Set to receive any incoming valid frames received, regardless of

its destination address. Default is set.

CA*

CApture Effect Mode: Set to enable an enhanced pick-off algorithm to avoid the net-

work capture effect.

PM*

Pass Multicast: Set to accept all multicast packets (not including the broadcast ad-

dress). Default is reset which directs all multicast address to hash table for further

filtering .

PB*

Pass Bad Frame: Set to enable GMAC to accept Runt frames defined by register 50.2

( RUNTSIZE). Default is reset. When PB=1, runt frame is accepted reguardless of

Reg32.3 (ARXERRB).

AB*

Accept Broadcast: Default is reset which yields control of all the broadcast addresses

to the check logic defined by register 32h bit 7, register 38h and 39h. Set to accept all

broadcast packets without any further address filtering.

HBD*

Reserved for test purpose. Default is 0.

RXINTC[1:0]* Receive Interrupt Counter : Receive interrupt RI or REI assertion depends on the num-

ber of packets received defined by these two bits or the RXINTT timer ( Reg.15/14h )

timeout, whichever comes first.

Default is 00h after reset, meaning the normal receive interrupt operation which as-

serts RI or REI after a single packet is received and no RXINTT timer is used. Non-

zero value in these two bits will enable this special receive interrupt operation.

RXINTC1 RXINTC0

Interrupt received packet count

0

0

1 ( default )

0

1

2

1

0

4

1

1

8

P/N:PM0723

REV. 1.0, JUL. 13, 2000

10

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