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MX98728EC

GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION

Macronix International 

MX98728EC

135

RDB

I, TTL

Host Bus Read Indicator : Active low. (Internal pull-up)

134

WRB

I, TTL

Host Bus Write Indicator : Active low. (Internal pull-up)

142

INTB

O/D, 4ma Host Bus Interrupt Output : Active low.

88

DREQB

O, 4ma

DMA Burst Read Request : Active low to request a burst

read transfer.

89

DACKB

I, TTL

DMA Read Acknowledge : Active low during the burst

read cycle.

130

RSTB

I,TTL

Host Bus Reset Input : Active low. (Schmidt trigger input,

Internal pull-up) Input delay is typically 7ns, minimum

RSTB pulse width must be 5 Tclk,Tclk=1/50MHz.

90

CSB

I,TTL

Host Bus Chip Select Input : Active low to enable access

to GMAC, set to disable access to GMAC. But the net-

work activity is independent of this signal. (Internal pull-

down)

91

H16_32

I,TTL

Host Bus Width 16 bit / 32 bit select : Set for the 16 bit

host bus, reset for the 32 bit host bus.

Packet Memory Interface

PIN#

46-43,

40,

38-35,

33-31,

29-25

46

Pin Name

MA[19:3]

MA19(RXD0)

45

MA18(RXD1)

44

MA17(RXD2)

43

MA16(RXD3)

24

MA2(EEDO)

Type

O,4ma

Description

Memory Address Bits 19-3:

I/O, 4ma

I/O, 4ma

I/O, 4ma

I/O, 4ma

I/O,4ma

Memory Address Bit19, when on-chip tranceiver is used,

it is defined as MA19, while in MII mode, it is used as receive

data bit RXD0 pin.

Memory Address Bit18, when on-chip tranceiver is used,

it is defined as MA18, while in MII mode, it is used as receive

data bit RXD1 pin.

Memory Address Bit17, when on-chip tranceiver is used,

it is defined as MA17, while in MII mode, it is used as receive

data bit RXD2 pin.

Memory Address Bit16, when on-chip tranceiver is used,

it is defined as MA16, while in MII mode, it is used as receive

data bit RXD3 pin.

Memory Address Bit 2 or EEPROM Data Out bit: Right after the

host reset, GMAC automatically load the configuration informa-

tion from the external EEPROM. During this period, MA2 pin

acts as an EEDO pin that reads in the output data stream from

the EEPROM. After the EEPROM auto load sequence is done,

this pin becomes MA2. Together with MA[19:3], they form the

packet buffer address lines 19 - 0.

P/N:PM0723

REV. 1.0, JUL. 13, 2000

6

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