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MX98728EC

GMAC SINGLE CHIP 10/100 FAST ETHERNET CONTROLLER FOR GENERIC APPLICATION

Macronix International 

MX98728EC

3.0 Register (Default value is defined after the hardware/power-up reset)

Reset logic : All register bits are cleared by the hardware reset, while the register bit with an "*" in its

symbol name is also cleared by the software reset.

Network Control Register A : NCRA (Reg0h), R/W, default=00h

Bit

Symbol

Description

0.0

RESET

Reset : Software reset. After hardware reset, this bit is 0 meaning normal operation. To

reset GMAC by software, software must write a 1 to this bit first, then followed by writing

a 0 to this bit. After writing a 0 to this bit, GMAC starts normal operation.

0.1

ST0*

Start Transmit Command/Status : Write to issue commands. When done, both bits are

0.2

ST1*

cleared automatically.

Transmit command : ST1 ST0

IDLE state

0 0 Read to indicate TX DMA idle state, write has no effect.

TX DMA Poll

0 1 Start TX DMA, send packets stored in packet memory.

TX FIFO Send

1 0 Immediately send the packet stored in the TX FIFO.

TX DMA Poll

1 1 Start TX DMA, send packets stored in packet memory.

0.3

0.4, 0.5

SR*

LB0*,LB1*

All transmit commands are cleared to 00 when the operation is done to indicate idle

state. When the TX DMA poll and the TX FIFO Send can not be used at the same time.

New packet can be written to the FIFO directly only when ST1, ST0=IDLE and

TXDMA[3:0]=1h. The TX DMA poll and the TX FIFO Send commands can be issued only

when ST1, ST0=IDLE and TXDMA[3:0]=1h, regardless of any error status in previous

transmission.

Start Receive : Enable the MAC to receive packets. Default is disabled.

Loop Back Mode: LB1 LB0

Mode0

0

0

Normal mode

Mode1

0

1

Internal FIFO Loopback

Mode2

1

0

Internal NWAY Loopback

Mode3

1

1

Internal PMD Loopback

Mode 2 and 3 are reserved for the IC test purpose. Only mode 1 can be used on the

bench. External loopback for the bench can be done by the full duplex normal mode with

the real cable hooked up from the TX port to the RX port.

0.6

INTMODE Interrupt Mode: Set for the active high interrupt, reset for the active low interrupt case.

0.7

INTCLK must be 0 for normal operation.

P/N:PM0723

REV. 1.0, JUL. 13, 2000

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