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LAN83C171

EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller

SMSC -> Microchip 

POWER DOWN MODE

The LAN83C171 has a power down feature

which allows it to consume less power when

not in use. The host may power down the

LAN83C171 by writing a 1 to the power down

bit in the general control register. When the

bit is set, the chip's internal system clock is

gated off to reduce switching current (the

transmit and receive clocks will be shut off

internally if the LAN83C171 is in loopback

mode when power down is set). While the

LAN83C171 is powered down, the host may

read and write the configuration registers or

the general control register. All other

functions are disabled (attempting any other

operation will cause unpredictable behavior).

The power down bit must only be set when the

LAN83C171 is in its idle state.

When the nRST pin is asserted, the

LAN83C171 will automatically enter power

down mode after recalling the contents of the

EEPROM. The host may power up the

LAN83C171 by writing a 0 to the power down

bit. If the host wishes to issue a software

reset to the LAN83C171, the power down bit

must be cleared. When the software reset has

completed, the power down bit will remain

cleared and the LAN83C171 will be ready to

operate.

The power down bit does not affect the PCI

clock inside the LAN83C171. Instead, the

LAN83C171 supports the PCI clock run

function which allows the host system to slow

down or temporarily shut off the PCI clock at

its source. The clock run function is

implemented according to the PCI Mobile

design guide (revision 1.0).

DMA OPERATION

The software driver controls the transmit and

receive DMA controllers through the I/O

control registers and through "buffer

descriptors" in host memory. There is an

independent chain (linked list) of descriptors for

each DMA. Each descriptor may point to a single

data buffer (which can hold a whole frame or

part of a frame) or to a fragment list, which in turn

contains a list of buffers for an entire frame. Each

descriptor also contains control and status

information and a pointer to the next descriptor.

The Descriptors Bit Description section explains

the bits in detail.

TRANSMIT DMA

The software driver initializes the transmit process

by writing the transmit control register, early

transmit threshold register (if early transmit will be

used), interpacket gap program register, interrupt

mask register and general control register. The

software must also program the PCI Transmit

Current Descriptor Address Register (PTCDAR)

with the address in host memory where the first

transmit descriptor will be located.

To begin packet transmissions, the software

driver programs the transmit descriptor chain with

the appropriate number of entries and then sets

the TXQUEUED bit in the COMMAND register.

Under no circumstances should the software

driver set up a circular transmit queue with a

single transmit descriptor pointing to itself. A

minimum of two descriptors is required for proper

EPIC operation.

Descriptor entries describe the location of transmit

data in host memory. Data for a single transmit

frame may not always be in a contiguous block in

host memory. The LAN83C171 allows the

software to specify multiple data buffers for each

frame. Each frame may be queued in one of two

ways, both of which may be used in the same

descriptor chain.

Direct Queuing Method

Descriptors point directly to the transmit data

buffers.

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