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LAN83C171

EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller

SMSC -> Microchip 

One or more descriptors may be used to point

to a single frame. All descriptors must have

the FRAGLIST control bit set to 0. The first

descriptor must contain the transmit length for

the frame. The last descriptor for the frame

must have the LASTDESCR bit set to 1 and

contain the desired values for the TXIAF and

NOCRC control bits. When the TXQUEUED

bit is set, the transmit DMA will read the 4

dword descriptor from the location in host

memory pointed to by its Current Descriptor

Address register. If the ownership bit in the

descriptor is equal to 1 then the LAN83C171

will accept the descriptor and update its

Current Descriptor Address register with the

value in the Next Descriptor Address field.

Otherwise, the TXQUEUED bit will be cleared

(and the transmit queue empty (TQE) interrupt

set) and the Current Descriptor Address

register will not be changed. The Transmit

Length field in the first descriptor will always

contain the number of bytes to be transmitted

on the network, and not necessarily the

number of bytes in the transmit buffers. The

transmit DMA will begin copying data from the

location in host memory specified by the

Buffer Address field in the first descriptor. It

will compare the transmit byte count to the

Data Length field, and copy the lesser number

of bytes into the local transmit RAM. If early

transmit is enabled, the LAN83C171 will

automatically initiate transmission on the

network when the number of bytes specified in

the Early Transmit Threshold register have

been loaded into the transmit buffer.

If the transmit byte count is less than the Data

Length field, or the LASTDESCR bit is set,

then the frame copy is complete after the

buffer has been read. The LAN83C171 will

initiate transmission on the network if it has

not already done so.

If the Data Length field is less than the

transmit byte count and the LASTDESCR bit is

not set, the LAN83C171 will attempt to read

another descriptor. The transmit DMA will

proceed as before, however this time it will not

read the Transmit Length field, but instead use the

remaining number of bytes in its transmit byte

counter (original byte count minus bytes already

copied). This process will continue until a

descriptor is read with the LASTDESCR bit set or

the transmit byte count reaches zero. If

LASTDESCR is set and the total number of bytes

copied do not add up to the transmit byte count,

the transmit MTU will pad the frame with random

data after copying all of the valid data out of the

transmit RAM. The CSMA/CD state machine will

not append the automatically generated CRC to

the frame if NOCRC is set in the last descriptor

for the frame.

After the LAN83C171 has initiated the first

transmission, it will check to see if there are any

more frames in the transmit queue. If the

software does not have another frame ready for

transmission, the ownership bit in the next

descriptor must be 0. If the ownership bit is 0, the

LAN83C171 will clear TXQUEUED and set the

transmit queue empty interrupt. If the ownership

bit is 1, the LAN83C171 will begin copying the

next frame into the local transmit RAM. The DMA

will continue copying transmit buffers until the

frame has been completely loaded into the

transmit RAM or the first transmission has

completed. If the copy completes while the first

transmission is still in progress, the LAN83C171

will stop and wait. When the transmission is

finished, the LAN83C171 will post the status into

the first descriptor for that frame and immediately

initiate the second transmission. If the

transmission completes before the copy is done,

the LAN83C171 will pause after the current

transmit buffer has been copied and post the

status from the first frame. If the early transmit

threshold has already been exceeded then the

second transmission will be initiated immediately.

The transmit DMA will then continue by reading

the next descriptor for the copy in progress.

When the transmit status is posted, the

ownership bit will be written as 0 to indicate that

the host now owns that descriptor again. The

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