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LAN83C171

EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller

SMSC -> Microchip 

post the receive status into the first descriptor

for the frame and set the receive copy complete

(RCC) interrupt. The DMA will read the next

descriptor and, if owned by the NIC, check to

see if there are any more frames to copy out of

the local RAM. If the receive DMA fills the first

host buffer before the entire frame has been

copied, it will read the next descriptor or

fragment list entry to find more buffer space.

This process will continue until the entire frame

has been copied. If the DMA reads a descriptor

with the ownership bit set to 0, it will clear the

RXQUEUED bit (and set the receive queue

empty interrupt) and wait for a new descriptor to

be queued. In fragment list mode, the receive

DMA always expects the fragment list to

contain enough buffer space for the entire

frame.

If all the buffers in the fragment list are filled

before the copy is finished, the DMA will abort

the copy and set the fragment list error bit in the

PRSTAT register. The DMA receive status will

be posted to the descriptor for that frame and

the RXQUEUED bit will be cleared. If early

receive is enabled, the network portion of the

receive status may not be valid yet, as indicated

by the RSV bit posted in the status. The

software driver may poll the RSV bit in the

interrupt status register, and when it returns a 1

read the receive status from PRSTAT. The

software may attempt to re-copy the frame by

setting the RXQUEUED bit again, or may

discard the frame by setting the NEXTFRAME

bit before or simultaneous to setting

RXQUEUED. If RXQUEUED is set after or

along with NEXTFRAME, the DMA will begin to

copy the next frame (if any) in the receive buffer.

Note: The DMA rounds the number of bytes

copied up to the nearest dword. If the receive

buffer does not start on a dword boundary, the

number of bytes in the receive buffer may be

slightly less (up to 3 bytes) than the receive

copy threshold when the interrupt is generated.

Adding Receive Buffers to the Pool

The software driver adds buffers to the pool by

writing the appropriate descriptors and setting

their ownership bit to 1. If the receive DMA has

stopped (RXQUEUED is cleared), the software

must set the RXQUEUED bit to queue the new

descriptors. The RXQUEUED bit may be set at

any time, even if the receive DMA is still active.

Receive Lookahead Method

When this buffering method is used, the

LAN83C171 first copies only the header of a

frame into host memory, and then waits for a

queue from the software driver before copying

the rest of the frame. The software usually

specifies the final destination of the frame data

with a fragment list. The advantage to this

buffering method is that the LAN83C171 may

copy frame data to its final destination instead

of a temporary buffer space, so the software

driver is not required to re-copy the data from

one host memory location to another.

In receive lookahead mode, frames are usually

copied into the host memory one at a time, and

a handshake is performed between the software

driver and the LAN83C171 during each frame.

The handshake is performed using the

RXQUEUED and NEXTFRAME bits in the

COMMAND register, the receive copy complete

(RCC), and header copy complete (HCC)

interrupts. The control bits in the receive

descriptors are also used to direct the receive

DMA.

The software driver begins by setting up a buffer

for the header of the first frame and setting

RXQUEUED. The HEADER control bit in the

descriptor should be set and the FRAGLIST bit

should be cleared. The buffer address pointer

and length are specified directly in the

descriptor. When a frame is received, the

receive DMA begins copying the beginning of

the frame into the header buffer until the buffer

is full, or until the entire frame has been copied.

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