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LAN83C171

EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller

SMSC -> Microchip 

buffer (fragment) is also 64 Kbytes. The

transmit DMA will run at the maximum PCI data

rate of 132 MByte/sec when the target memory

system supports zero wait state reads. The

transmit DMA will burst as many words as it can

before having to relinquish the PCI bus. It is

capable of bursting data continuously with no

wait states (even when a transmission is active

on the network) until the transmit RAM becomes

full. The transmit DMA, however, will most

likely lose possession of the PCI bus several

times before it can fill the entire 1.5 Kbyte

transmit buffer.

RECEIVE DMA

The software driver initializes the receive

process by writing the receive control register,

interrupt mask register and general control

register. The software must also program the

PCI Receive Current Descriptor Address

Register (PRCDAR) with the address in host

memory where the first receive descriptor will be

located.

To allow packet receptions, the software driver

programs the receive descriptor chain and then

sets the RXQUEUED and START_RX bits in the

COMMAND register. Setting START_RX brings

the CSMA/CD receiver online. The receive DMA

is enabled by setting RXQUEUED. The

software driver should set RXQUEUED before

or simultaneous to bringing the receiver online

so that the receiver does not overflow the local

buffer while waiting for a descriptor to be

queued. The first descriptor must be valid

before the RXQUEUED bit is set. The first

descriptor will be read as soon as it is queued,

even if no receptions have occurred on the

network.

The receive lookahead method offers maximum

performance in most cases.

Free Buffer Pool Method

In this mode the software driver pre-allocates a

pool of free buffers for frames received by the

LAN83C171. The ONECOPY bit in the general

control register must be set so that the each

frame may be copied into the buffer pool without

host intervention. The descriptors for the free

buffer pool may point directly to the buffers, or

point to a fragment list which in turn specifies

the buffers.

When the RXQUEUED bit is set, the receive

DMA will attempt to read the first descriptor

from the address pointed to by its Current

Descriptor Address register. If the ownership bit

is 0, the RXQUEUED bit will be cleared (and the

receive queue empty (RQE) interrupt set) and

the Current Descriptor Address register will not

be changed. If the ownership bit is equal to 1,

the LAN83C171 will accept the descriptor and

update its Current Descriptor Address register

with the value in the Next Descriptor Address

field. The LAN83C171 will save the descriptor

information until a frame is received. If the

fraglist control bit is also 1, then the receive

DMA will read and save the address pointer and

data length for the first buffer in the fragment

list. The offset field in the descriptor (see buffer

length field) should be set to zero, otherwise the

copy will not begin at the start of the frame. The

fragment list format for the receive DMA is

identical to the format for the transmit DMA.

As soon as a frame is received, the LAN83C171

will begin copying it from the local receive

buffer into the allocated buffer in host memory.

If early receive is enabled, the LAN83C171 can

begin the copy while reception is still in

progress. The receive DMA always monitors the

local buffer contents so that a receive underflow

can never occur. As soon as the receive DMA

has copied the number of bytes in the PCI

Receive Copy Threshold register, it will set the

receive copy threshold (RCT) interrupt. When

the receive DMA has copied the entire packet

from the local RAM into host memory, it will

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