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LAN83C171

EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller

SMSC -> Microchip 

the descriptors are written, the TXQUEUED bit

should be set.

TXQUEUED can be written regardless of

completion status and will ensure that the latest

frame is transmitted. If the LAN83C171

reaches the end of the transmit queue before the

new frame has been added, a transmit chain

complete interrupt is generated for the old

portion of the queue and another transmit chain

complete interrupt will be generated when the

added portion completes.

Interrupting Transmit Chain

The host may interrupt the transmit chain before

all frames have been transmitted by setting the

STOP_TDMA bit in the command register.

Setting this bit forces TXQUEUED to 0. The

transmit DMA will finish copying any frame that

it has already begun, and transmit all frames

that have been loaded into the transmit ram.

After the transmit DMA has posted the status

for the last frame, it will set the transmit chain

complete interrupt and return to its idle state

(exactly as if the next frame in the queue was

owned by the host). If the DMA reads a

descriptor owned by the host while a copy is still

in progress, it will set the transmit queued empty

interrupt and wait for the descriptor to be re-

queued. It will not return to the idle state until

the copy is completed.

Transmit Buffer Full

Whenever the local transmit RAM becomes full,

the transmit DMA will wait until more space is

available before loading any more data. Space

is freed up as the transmit MTU reads data from

the local RAM and updates its pointers. In

some cases, the transmit MTU will leave its

pointers at the beginning of a frame until it

knows that the transmission will not have to be

retried. Automatic retries can occur due to

collisions or early transmit underruns.

Transmit Underrun

A transmit underrun occurs in early transmit

mode when the transmit DMA cannot keep up

with transmission on the network. Data must be

read from the local RAM before it is available.

Usually, when an underrun occurs, the transmit

MTU will generate a transmit underrun (TXU)

interrupt and update its transmit status register.

The transmit DMA will continue to operate as

though nothing has happened. The software

driver will be allowed to read the transmit status

value from TXSTAT and set the "transmit

underrun go" (TXUGO) bit to tell the MTU to

retry the frame. The MTU will re-transmit the

entire frame out of the local transmit ram. When

transmission has completed successfully, the

DMA will post the transmit status for the retry to

the descriptor for that frame. Operation will

continue as it normally would for a non-underrun

situation.

Exception to Underrun ReTransmission

The only exception to this behavior is when the

transmit MTU cannot automatically retry an

underrun frame. This happens when the frame

size is larger than the transmit RAM (1.5

Kbytes) and the transmit DMA has overwritten

the beginning of the frame before the underrun

occurs. If such an event occurs, the transmit

DMA will abort the copy and reset its pointers to

the first descriptor for that frame. The DMA will

clear the TXQUEUED bit and return to its idle

state. Transmit queue empty and transmit

chain complete interrupts will be generated

along with the transmit underrun interrupt. The

software driver must set TXUGO to reset the

transmit MTU and then set TXQUEUED if it

wants to retry the frame. The frame will be

re-copied from scratch out of host memory

when TXQUEUED is set.

Maximum Transmit Size and Burst Rate

The transmit DMA supports frame sizes up to 64

Kbytes. The maximum size for a single data

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