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UPD72850A

IEEE1394 400Mbps PHY

NEC => Renesas Technology 

µPD72850A

• The µPD72850A activates the PHY/Link interface when LPS is 1, regardless of the value of the Link active bit.

4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7)

The PHY/Link Interface consists of the following operations:

• Status transfer to the Link layer controller by CTL

• Transmit packet

• Receive packet

• Request from the Link layer controller by LREQ

4.3.1 CTL0,CTL1

CTL0,CTL1 controls the PHY/Link interface as shown in the Table 4-3.

CTL0,CTL1

00

01

10

11

Type

Idle

Status

Receive

Grant

Table 4-3. CTL Controls PHY

Content

PHY is in idle function

PHY transmitting status information to Link

PHY receiving data from the Link

PHY allows Link to transmit data

This is the operation by which, after Grant, the Link obtains the right to control the interface.

CTL0,CTL1

00

01

Idle

Hold

Type

10

Transmit

11

-

Table 4-4. CTL Controls Link

Content

Link completes the packet transmission and releases the PHY/Link interface.

1) Link transmits Hold until the data is ready for transmission.

2) Link transmits the interface connect packet.

Link transmits the data to PHY.

Not used.

4.3.2 LREQ

Access to the PHY register and the bus is controlled from the Link layer controller through the LREQ pin of PHY.

LREQ

Figure 4-3. LREQ and CTL Timing

LR0 LR1 LR2 LR3

LR(n-2) LR(n-1)

CTL0,CTL1

CA

CB

CA : CTL before generation of LREQ

CB : CTL during LREQ execution

Data Sheet S14452EJ1V0DS00

23

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