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UPD72850A

IEEE1394 400Mbps PHY

NEC => Renesas Technology 

µPD72850A

Table 4-11. PHY Operation Before LREQ Request to the CTL Function Changes

Request

Fair, Priority

State of CTL in C B after

LREQ was issued

Receive

Immediate

Isochronous

Register Read

Register Write,

Acceleration

control

Grant

Idle, Status

Grant

Receive

Idle, Status

Transmit Idle (driven by Link)

Grant

Receive

Status

Idle

Any (driven by Link)

Grant

Receive

Status

Idle

Any

Operation of the PHY (µPD72850A)

• Hold the request if the acceleration of arbitration packet transmitted with

enable is 8 bits (ACK).

Except for 8 bits, the requests are ignored.

• Ignore the request when the acceleration of arbitration is disabled.

Arbitration Won.

Excluding when the bus reset is generated, Hold the requests.

The packet is being transmitted to Link. Request Hold.

Excluding when the bus reset is generated, hold the request.

Request Hold.

Arbitration Won.

Request Hold.

Request is ignored when sub-action gap is detected.

Request Hold.

Request Hold.

Hold the request until the corresponding register value is returned.

Request is completed.

4.3.3 PHY/Link Interface Timing

(1) SCLK timing

Table 4-12. SCLK Timing

Timing Constant

BUS_TO_LINK_DELAY

DATA_PREFIX_TO_GRANT

LINK_TO_BUS_DELAY

MAX_HOLD

Comment

Period from receiving RX_DATA_PREFIX until

Receive to CTL is output.

Period when the Grant is output to CTL after

TX_DATA_PREFIX is output to a port.

Period when TX_DATA_END is output to all ports

after transmitting the packet by Link after idle was

asserted to CTL.

Maximum period when Hold can be asserted by Link

to confirm Grant.

MIN.

2

2

MAX.

9

Unit

SCLK cycle

25

SCLK cycle

5

SCLK cycle

47

SCLK cycle

Data Sheet S14452EJ1V0DS00

27

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