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UPD72850A

IEEE1394 400Mbps PHY

NEC => Renesas Technology 

µPD72850A

The bus request (ImmReq, IsoReq, PriReg, FairReq) is completed (in case of ImmReq, IsoReq, when the

subaction gap is detected) when the packet is transmitted or canceled by canceling the bus request.

(2) LREQ rules

The Link request and the status of the serial bus are asynchronous; the bus request can be canceled by the

status of the serial bus.

The following rules apply to a request by LREQ:

• Link cannot issue a bus request (ImmReq, IsoReq, PriReq, FairReq) if Grant is given to an LREQ request or

until the Link’s request is canceled. The request can be canceled by the µPD72850A if it detects subaction

gap at ImmReq, IsoReq.

• Do not issue a RdReg or WrReg request when the status transmission is not completed by the Read request

register.

• All of the bus requests (ImmReq, IsoReq, PriReq, FairReq) are canceled by a bus reset.

In addition, there is a limitation in the request of LREQ according to the state of CTL as shown in Table 4-10.

Table 4-10. Rules for Other Requests

Request

Fair, Priority

Immediate

Isochronous

Register Read

Register Write

AccCtrl

State of CTL in CA to

LREQ issues

which LREQ is allowed permission when Link

when PHY drives CTL

drives CTL

Idle, Status

wrong

Receive, Idle

wrong

any

correct

any

correct

any

correct

Note

Fair, Priority request cannot be issued until the

unprocessed bus request is completed.

Link issues the request after completing the decoding of

Destination_ID, when the acknowledge packet is ready.

After the packet is received, it is necessary to transmit the

first bit of the request within four cycles.

If the isochronous packet transmission is prepared for the

isochronous period, it is issued.

Do not issue the request to transmit the isochronous

packet appending to the currently transmitted isochronous

packet (Using Hold).

Do not issue this request if the unprocessed Read request

has not been completed.

To set acceleration bit 0:

When the isochronous period starts, if the Enab_accel bit

is one, Cycle slave should adjust accelerate bit to 0.

To set acceleration bit 1:

Do not set the cycle master.

It is issued when the isochronous period ends.

26

Data Sheet S14452EJ1V0DS00

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