UPD72850A Ver la hoja de datos (PDF) - NEC => Renesas Technology
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UPD72850A Datasheet PDF : 48 Pages
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µPD72850A
(2) AC timing
Table 4-13. PHY/Link Interface Timing
Parameter
D, CTL propagation delay
D, CTL, LREQ setup time
D, CTL, LREQ Hold time
Symbol
MIN.
MAX.
Unit
tpd
0.5
13.5
ns
tsu
6
ns
th
0
ns
Figure 4-4. PHY/Link Interface AC Timing
SCLK
tpd
tpd
tpd
D, CTL
SCLK
tsu
th
D, CTL, LREQ
4.4 Acceleration Control
Enable of ack-acceleration and fly-by on the same isochronous period may create a problem. The isochronous
cycle may extend unintentionally when transmitting the asynchronous packet by a node using ack-acceleration and
fly-by.
To avoid this problem, Link should control Disable/Enable of these enhancements (ack-Acceleration, fly-by), by
Acceleration Control requests. Cycle master cannot issue the Acceleration Control request.
The enhancements should not be used from the generation of the local cycle synchronization event to the
confirmation of cycle start. In this period, all Links except for Cycle Master use Acceleration Control as follows:
• Do not issue Fair nor Priority request to Link after generating local cycle synchronization, if the Acceleration
Control request’s Accelerate bit is not set to 0.
• Link must not use Hold when transmitting continuous primary asynchronous packet after the Acknowledge
packet, except after ack_pending to complete the split transaction.
• Ending the Link during the isochronous period issues the acceleration control request to set the Accelerate bit to
1, enabling these enhancements.
The µPD72850A does not require setting the Acceleration Control during isochronous transmit to enable the
isochronous request fly-by acceleration.
It is not necessary to issue Acceleration Control request when the cycle master is absent from the serial bus.
These enhancements are enabled if the Enab_accel bit in the PHY register is set. The µPD72850A supports Variable
Acceleration controlled by the Acceleration Control during power-on reset.
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Data Sheet S14452EJ1V0DS00
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