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AD9396

Analog/DVI Dual-Display Interface

Analog Devices 

TIMING

The output data clock signal is created so that its rising edge

always occurs between data transitions and can be used to latch

the output data externally.

There is a pipeline in the AD9396, which must be flushed

before valid data becomes available. This means 23 data sets are

presented before valid data is available.

The timing diagram in Figure 7 shows the operation of the

AD9396.

tPER

tDCYCLE

DATACK

DATA

HSOUT

tSKEW

Figure 7. Output Timing

HSYNC Timing

Horizontal sync (HSYNC) is processed in the AD9396 to

eliminate ambiguity in the timing of the leading edge with

respect to the phase-delayed pixel clock and data.

The HSYNC input is used as a reference to generate the pixel

sampling clock. The sampling phase can be adjusted, with

respect to HSYNC, through a full 360° in 32 steps via the phase

adjust register (to optimize the pixel sampling time). Display

systems use HSYNC to align memory and display write cycles,

so it is important to have a stable timing relationship between

the HSYNC output (HSOUT) and data clock (DATACK).

AD9396

Three things happen to HSYNC in the AD9396. First, the

polarity of HSYNC input is determined and thus has a known

output polarity. The known output polarity can be programmed

either active high or active low (Register 0x24, Bit 7). Second,

HSOUT is aligned with DATACK and data outputs. Third, the

duration of HSOUT (in pixel clocks) is set via Register 0x23.

HSOUT is the sync signal that should be used to drive the rest

of the display system.

Coast Timing

In most computer systems, the HSYNC signal is provided con-

tinuously on a dedicated wire. In these systems, the coast input

and function are unnecessary, and should not be used. The pin

should be permanently connected to the inactive state.

In some systems, however, HSYNC is disturbed during the

vertical sync period (VSYNC). In some cases, HSYNC pulses

disappear. In other systems, such as those that employ

composite sync (Csync) signals or embedded SOG, HSYNC

includes equalization pulses or other distortions during

VSYNC. To avoid upsetting the clock generator during VSYNC,

it is important to ignore these distortions. If the pixel clock PLL

sees extraneous pulses, it attempts to lock to this new frequency,

and changes frequency by the end of the VSYNC period. It then

takes a few lines of correct HSYNC timing to recover at the

beginning of a new frame, tearing the image at the top of the

display.

The coast input is provided to eliminate this problem. It is an

asynchronous input that disables the PLL input and allows the

clock to free-run at its then-current frequency. The PLL can

free-run for several lines without significant frequency drift.

Coast can be generated internally by the AD9396 (see

Register 0x12[1]), can be driven directly from a VSYNC input,

or can be provided externally by the graphics controller.

Rev. 0 | Page 15 of 48

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