AD9396 Ver la hoja de datos (PDF) - Analog Devices
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AD9396 Datasheet PDF : 48 Pages
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AD9396
The functional diagram for a single channel of the CSC, as
shown in Figure 13, is repeated for the remaining G and B
channels. The coefficients for these channels are b1, b2, b3, b4,
c1, c2, c3, and c4.
A programming example and register settings for several
common conversions are listed in the Color Space Converter
(CSC) Common Settings.
For a detailed functional description and more programming
examples, refer to the application note AN-795, AD9880 Color
Space Converter User's Guide.
TIMING DIAGRAMS
The following timing diagrams show the operation of the
AD9396.The output data clock signal is created so that its rising
edge always occurs between data transitions and can be used to
latch the output data externally. There is a pipeline in the
AD9396, which must be flushed before valid data becomes
available. This means six data sets are presented before valid
data is available.
a1[12:0]
RIN [11:0]
×
×
1
4096
+
a2[12:0]
BIN [11:0]
×
a3[12:0]
×1
4096
a4[12:0]
+
+
CSC_Mode[1:0]
×4
2
ROUT [11:0]
×2
1
0
GIN [11:0]
×
×
1
4096
Figure 13. Single CSC Channel
DATAIN
HSIN
DATACK
DATAOUT
HSOUT
P0 P1 P2
P3
P4
P5
P6 P7
P8
P9 P10 P11
2 CLOCK CYCLE DELAYS
8 CLOCK CYCLE DELAYS
P0
P1
P2
P3
Figure 14. RGB ADC Timing
DATAIN
HSIN
P0 P1 P2
P3
P4
P5
P6 P7
P8
P9 P10 P11
Table 11.
Port
Bit
4:4:4
4:2:2
4:4:4 DDR
4:2:2 to 12
DATACK
YOUT
8 CLOCK CYCLE DELAYS
Y0
Y1
Y2
Y3
CB/CROUT
HSOUT
2 CLOCK CYCLE DELAYS
B0
R0
B2
R2
NOTES:
1. PIXEL AFTER HSOUT CORRESPONDS TO BLUE INPUT.
2. EVEN NUMBER OF PIXEL DELAYS BETWEEN HSOUT AND DATAOUT.
Figure 15. YCrCb ADC Timing
Red
Green
Blue
7654 321076543210
765 4 3 2 1 0
Red/Cr [7:0]
Green/Y [7:0]
Blue/Cb [7:0]
CbCr [7:0]
Y [7:0]
DDR 4:2:2 ↑ CbCr ↓ Y, Y
DDR ↑ 1 G [3:0]
DDR ↑ B [7:4]
DDR ↑ B [3:0]
DDR 4:2:2 ↑ CbCr [11:0]
DDR ↓ R [7:0]
DDR ↓ G [7:4]
DDR 4:2:2 ↓ Y,Y [11:0]
CbCr [11:0]
Y [11:0]
1 Arrows in the table indicate clock edge. Rising edge of clock = ↑, falling edge = ↓.
Rev. 0 | Page 20 of 48
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