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AD9396

Analog/DVI Dual-Display Interface

Analog Devices 

AD9396

Sync Slicer

The purpose of the sync slicer is to extract the sync signal from

the green graphics or luminance video signal that is connected

to the SOGIN input. The sync signal is extracted in a two-step

process. First, the SOG input (typically 0.3 V below the black

level) is detected and clamped to a known dc voltage. Next, the

signal is routed to a comparator with a variable trigger level (set

by Register 0x1D, Bits [7:3]), but nominally 0.128 V above the

clamped voltage. The sync slicer output is a digital composite

sync signal containing both HSYNC and VSYNC information

(see Figure 9).

Sync Separator

As part of sync processing, the sync separator’s task is to extract

VSYNC from the composite sync signal. It works on the idea

that the VSYNC signal stays active for a much longer time than

the HSYNC signal. By using a digital low-pass filter and a

digital comparator, it rejects pulses with small durations (such

as HSYNCs and equalization pulses) and only passes pulses

with large durations, such as VSYNC (see Figure 9).

The threshold of the digital comparator is programmable for

maximum flexibility. To program the threshold duration, write

a value (N) to Register 0x11. The resulting pulse width is

N × 200 ns. So if N = 5, the digital comparator threshold is 1 μs.

Any pulses less than 1 μs are rejected, while any pulse greater

than 1 μs passes through.

The sync separator on the AD9396 is simply an 8-bit digital

counter with a 6 MHz clock. It works independently of the

polarity of the composite sync signal. Polarities are determined

elsewhere on the chip. The basic idea is that the counter counts

up when HSYNC pulses are present. But because HSYNC

pulses are relatively short in width, the counter only reaches a

value of N before the pulse ends. It then starts counting down

until eventually reaching 0 before the next HSYNC pulse

arrives. The specific value of N varies for different video modes,

but is always less than 255. For example, with a 1 μs width

HSYNC, the counter only reaches 5 (1 μs/200 ns = 5). Now,

when VSYNC is present on the composite sync the counter also

counts up. However, because the VSYNC signal is much longer,

it counts to a higher number, M. For most video modes, M is at

least 255. So VSYNC can be detected on the composite sync

signal by detecting when the counter counts to higher than N.

The specific count that triggers detection, T, can be

programmed through the Serial Register 0x11.

Once VSYNC has been detected, there is a similar process to

detect when it goes inactive. At detection, the counter first

resets to 0, then starts counting up when VSYNC finishes. As in

the previous case, it detects the absence of VSYNC when the

counter reaches the threshold count, T. In this way, it rejects

noise and/or serration pulses. Once VSYNC is detected to be

absent, the counter resets to 0 and begins the cycle again.

There are two things to keep in mind when using the sync

separator. First, the resulting clean VSYNC output is delayed

from the original VSYNC by a duration equal to the digital

comparator threshold (N × 200 ns). Second, there is some

variability to the 200 ns multiplier value. The maximum varia-

bility over all operating conditions is ±20% (160 ns to 240 ns).

Because normal VSYNC and HSYNC pulse widths differ by a

factor of about 500 or more, 20% variability is not an issue.

700mV MAXIMUM

SOGIN

+300mV

0mV

–300mV

SOGOUT OUTPUT

CONNECTED TO

HSIN

NEGATIVE PULSE WIDTH = 40 SAMPLE CLOCKS

COMPOSITE

SYNC

AT HSIN

VSOUT

FROM SYNC

SEPARATOR

Figure 9. Sync Slicer and Sync Separator Output

Rev. 0 | Page 17 of 48

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