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AD9396

Analog/DVI Dual-Display Interface

Analog Devices 

AD9396

Sync Processing

The inputs of the sync processing section of the AD9396 are

combinations of digital HSYNCs and VSYNCs, analog sync-on-

green, or sync-on-Y signals, and an optional external coast

signal. From these signals, it generates a precise, jitter-free (9%

or less at 95 MHz) clock from its PLL; an odd/even field signal;

HSYNC and VSYNC out signals; a count of HSYNCs per

VSYNC; and a programmable SOG output. The main sync

processing blocks are the sync slicer, sync separator, HSYNC

filter, HSYNC regenerator, VSYNC filter, and coast generator.

The sync slicer extracts the sync signal from the green graphics

or luminance video signal that is connected to the SOGIN input

and outputs a digital composite sync. The sync separator’s task

is to extract VSYNC from the composite sync signal, which can

come from either the sync slicer or the HSYNC input. The

HSYNC filter is used to eliminate any extraneous pulses from

the HSYNC or SOGIN inputs, outputting a clean, low jitter

signal that is appropriate for mode detection and clock

generation. The HSYNC regenerator is used to re-create a clean,

although not low jitter, HSYNC signal that can be used for

mode detection and counting HSYNCs per VSYNC. The

VSYNC filter is used to eliminate spurious VSYNCs, maintain a

stable timing relationship between the VSYNC and HSYNC

output signals, and generate the odd/even field output. The

coast generator creates a robust coast signal that allows the PLL

to maintain its frequency in the absence of HSYNC pulses.

HSYNC 0

HSYNC 1

SOGIN 0

SOGIN 1

VSYNC 0

VSYNC 1

COAST

CHANNEL

SELECT

[0x11:3]

HSYNC

SELECT

[0x11:7]

AD1

PD2

MUX

MUX

HSYNC FILTER

AND

REGENERATOR

AD1

PD2

SYNC

SLICER

AD1

SYNC

SLICER

AD1

AD1

PD2

MUX

FH4

SP SYNC FILTER EN

0x21:7

VSYNC

MUX

SYNC

PROCESSOR

AND

VSYNC FILTER

MUX

RH3

MUX

SP5

SOGOUT SELECT

0x24:2,1

VSYNC

FILTERED

VSYNC

MUX

SOG OUT

VSYNC OUT

AD1

PD2

FILTER COAST VSYNC

0x12:0

PLL SYNC FILTER EN

0x21:6

MUX

HSYNC

VSYNC FILTER EN

0x21:5

HSYNC/VSYNC

COUNTER

SP5

REG 26H, 27H

O/E

FIELD

AD9396

COAST

MUX

PLL CLOCK

GENERATOR

COAST SELECT

0x12:1

SP5

HSYNC OUT

SP5

DATACK

1ACTIVITY DETECT

2POLARITY DETECT

3REGENERATED HSYNC

4FILTERED HSYNC

5SET POLARITY

Figure 8. Sync Processing Block Diagram

Rev. 0 | Page 16 of 48

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