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MTD800

Integrated Fast Ethernet Controller

Myson Century Inc 

MYSON

TECHNOLOGY

MTD 800

(Preliminary)

Name

CBE#[3:0]

IDSEL

FRAME#

IRDY#

TRDY#

DEVSEL#

STOP#

INTA#

PAR

GNT#

REQ#

PERR#

PME#

COL

RXDV

TXCK

TXD[3:0]

TXEN

RXCK

Pin #

11, 25,

33, 44

12

26

27

28

29

30

121

32

126

127

31

128

104

120

119

115 -

118

114

111

I/O

Descriptions

4-bit multiplexed bus command and byte enables. During the address

I/O phase transaction, CBE is considered as bus command. On the data phase

cycles, CBE represents the byte enable signals for PCI data bus.

I Used as a chip select during access to the configuration registers

Driven by MTD800 to Indicate the start and duration of a transaction. The

I/O FRAME# is deasserted when the master is ready to complete the final data

phase in the transaction.

During a write transaction, the current bus master asserts IRDY# to indicate

that valid data is being driven onto the PCI bus. During a read transaction,

I/O this signal is asserted to indicate that the master is ready to accept data

from the selected target. Wait states are inserted until both IRDY# and

TRDY# are asserted.

During a read transaction, the target asserts TRDY# to indicate that valid

data is being driven onto the PCI bus. During a write transaction, this signal

I/O is asserted to indicate that the target is ready to accept data. TRDY# is

used in conjunction with IRDY#. A data phase is completed on any clock

when both IRDY# and TRDY# are asserted.

Asserted by MTD800 to indicate that the device has decoded the address

I/O as the target of current access. As an input, DEVSEL# indicates whether

any device on the bus has been selected.

Asserted by MTD800 to disconnect any further transaction. As an input,

I/O DEVSEL# indicates whether any device on the bus or bridge has termi-

nated the transaction.

O/D INTA# is an asynchronous signal which is used to request an interrupt.

Ensures even parity across AD[31:0] and CBE[3:0]. PAR is stable and valid

I/O

for one clock after the address phase. During the data phase, PAR is stable

and valid for one clock after either IRDY#(write transaction) or TRDY#(read

transaction) is asserted.

I

Asserted by the PCI bus arbiter to indicate that MTD800 has granted the

bus control authority.

O/Z

Asserted by MTD800 to signal bus arbiter that it needs the dedicated

access to the PCI bus.

I/O PERR# is asserted when a data parity error is detected.

O/D

An interrupt signal for the occurrence power management event. Asserted

by MTD800 to request a change in the device or system power state.

Network Interface

I

Collision signal. COL is asserted high when PHY detects a collision on the

medium. This signal is asynchronous to TXCK or RXCK.

I

Receive data valid. RXDV is asserted high by PHY to indicate the incoming

receive data RXD[3:0] is valid. This signal is synchronous to RXCK.

I

Transmit Clock. TXCK is a continuous clock that provides the timing refer-

ence for the transfer of the TXD[3:0] and TXEN signals.

O

Transmit Data signals. TXD are driven by MTD800 and transits synchro-

nously with respect to the TXCK.

O

Transmit Data Enable. TXEN is driven by MTD800 and transits synchro-

nously with respect to the TXCK.

I

Receive Clock. RXCK is a continuous clock that provides the timing refer-

ence for the transfer of the RXD[3:0], RXDV and RXER.

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MTD800 Revision 0.0 07/20/1999

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