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HEF4517B_09

Dual 64-bit static shift register

NXP Semiconductors. 

NXP Semiconductors

HEF4517B

Dual 64-bit static shift register

a. Input waveforms

VI 90 %

tW

negative

pulse

VM

10 %

0V

tf

VI

positive

pulse

tr

90 %

VM

10 %

0V

tW

VM

tr

tf

VM

001aaj781

VI

G

VDD

VO

DUT

VEXT

RL

RT

CL

001aaj915

b. Test circuit

Fig 8.

Test data is given in Table 10.

Definitions for test circuit:

RL = Load resistance;

CL = Load capacitance including jig and probe capacitance;

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

Test circuit for switching times

Table 10. Test data

Supply

voltage

Input

VI

5 V to 15 V VDD

tr, tf

≤ 20 ns

Load

CL

50 pF

RL

1 kΩ

VEXT

tPLH, tPHL

open

tPLZ, tPZL

2VDD

tPHZ, tPZH

GND

HEF4517B_6

Product data sheet

Rev. 06 — 10 December 2009

© NXP B.V. 2009. All rights reserved.

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