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HEF4517B_09

Dual 64-bit static shift register

NXP Semiconductors. 

NXP Semiconductors

HEF4517B

Dual 64-bit static shift register

Table 8. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.

Symbol Parameter

VDD

Typical formula for PD (μW)

where:

PD

dynamic power 5 V

PD = 7000 × fi + Σ(fo × CL) × VDD2

fi = input frequency in MHz,

dissipation

10 V

PD = 28000 × fi + Σ(fo × CL) × VDD2

fo = output frequency in MHz,

15 V

PD = 70000 × fi + Σ(fo × CL) × VDD2

CL = output load capacitance in pF,

VDD = supply voltage in V,

Σ(fo × CL) = sum of the outputs.

12. Waveforms

VI

nCP input

VM

0V

VOH

tPHL

tPLH

nQn output

VM

VOL

001aaj914

Fig 4.

Measurement points are given in Table 9

The logic levels VOH and VOL are typical voltage output levels that occur with the output load.

Propagation delays for nCP to nQn

Table 9.

Input

VM

0.5VI

Measurement points

Output

VM

0.5VDD

VX

0.1VDD

VY

0.9VDD

HEF4517B_6

Product data sheet

Rev. 06 — 10 December 2009

© NXP B.V. 2009. All rights reserved.

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