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HEF4517B_09 Datasheet PDF : 15 Pages
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NXP Semiconductors
HEF4517B
Dual 64-bit static shift register
11. Dynamic characteristics
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Extrapolation formula
tPHL
HIGH to LOW
nCP to nQn;
5 V [1] 193 ns + (0.55 ns/pF)CL
propagation delay see Figure 4
10 V
74 ns + (0.23 ns/pF)CL
15 V
52 ns + (0.16 ns/pF)CL
tPLH
LOW to HIGH
nCP to nQn;
5 V [1] 163 ns + (0.55 ns/pF)CL
propagation delay see Figure 4
10 V
64 ns + (0.23 ns/pF)CL
15 V
42 ns + (0.16 ns/pF)CL
tPHZ
HIGH to OFF-state nPE/OE to nQn; 5 V
propagation delay see Figure 5
10 V
15 V
tPZH
OFF-state to HIGH nPE/OE to nQn; 5 V
propagation delay see Figure 5
10 V
15 V
tPLZ
LOW to OFF-state nPE/OE to nQn; 5 V
propagation delay see Figure 5
10 V
15 V
tPZL
OFF-state to LOW nPE/OE to nQn; 5 V
propagation delay see Figure 5
10 V
15 V
tt
transition time
nQn;
5 V [1] 10 ns + (1.00 ns/pF)CL
see Figure 6
10 V
9 ns + (0.42 ns/pF)CL
15 V
6 ns + (0.28 ns/pF)CL
tsu
set-up time
nQn, nD to nCP; 5 V
see Figure 7
10 V
15 V
th
hold time
nQn, nD to nCP; 5 V
see Figure 7
10 V
15 V
tW
pulse width
nQn, nD to nCP; 5 V
see Figure 7
10 V
15 V
fmax
maximum
frequency
see Figure 7
5V
10 V
15 V
Min Typ Max Unit
-
220 440 ns
-
85 170 ns
-
60 120 ns
-
190 380 ns
-
75 150 ns
-
50 100 ns
-
40
80 ns
-
30
60 ns
-
25
50 ns
-
45
90 ns
-
25
50 ns
-
20
40 ns
-
50 100 ns
-
30
60 ns
-
25
50 ns
-
60 120 ns
-
30
60 ns
-
25
50 ns
-
60 120 ns
-
30
60 ns
-
20
40 ns
30 10 -
ns
25
5-
ns
20
5-
ns
45 15 -
ns
30 10 -
ns
25 10 -
ns
-
95 190 ns
-
40
80 ns
-
30
60 ns
2
5-
MHz
6
12 -
MHz
8
16 -
MHz
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
HEF4517B_6
Product data sheet
Rev. 06 — 10 December 2009
© NXP B.V. 2009. All rights reserved.
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