HEF4517B_09 Ver la hoja de datos (PDF) - NXP Semiconductors.
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HEF4517B_09 Datasheet PDF : 15 Pages
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NXP Semiconductors
HEF4517B
Dual 64-bit static shift register
7. Functional description
Table 3. Function table[1]
Inputs
Inputs/outputs
Mode
nCP nD
nPE/OE nQ16
nQ32
nQ48
nQ64
↑ data entered L
into 1st bit
content of
16th bit
displayed
content of
32nd bit
displayed
content of
48th bit
displayed
content of
64th bit
displayed
One 64-bit shift register. The
content of the shift register is
shifted over one stage
↑ data entered H
into 1st bit
data at nQ16 data at nQ32 data at nQ48 remains in ‘Z’ Four 16-bit shift register. The
entered into entered into entered into state
content of the shift registers is
17th bit
33rd bit
49th bit
shifted over one stage
↓X
L
no change no change no change no change no change
↓X
H
Z
Z
Z
Z
no change
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance state;
↑ = positive-going transition; ↓ = negative-going transition.
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDD
IIK
VI
IOK
II/O
IDD
Tstg
Tamb
Ptot
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
VI < −0.5 V or VI > VDD + 0.5 V
VO < −0.5 V or VO > VDD + 0.5 V
DIP16 package
SO16 package
P
power dissipation
per output
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
Min
−0.5
-
−0.5
-
-
-
−65
−40
[1] -
[2] -
-
Max
Unit
+18
V
±10
mA
VDD + 0.5 V
±10
mA
±10
mA
50
mA
+150
°C
+85
°C
750
mW
500
mW
100
mW
HEF4517B_6
Product data sheet
Rev. 06 — 10 December 2009
© NXP B.V. 2009. All rights reserved.
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