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HEF4517B_09

Dual 64-bit static shift register

NXP Semiconductors. 

NXP Semiconductors

HEF4517B

Dual 64-bit static shift register

VI

nPE/OE input

0V

VDD

nQn output

LOW-to-OFF

OFF-to-LOW

VOL

nQn output

HIGH-to-OFF

OFF-to-HIGH

VOH

GND

VM

tPLZ

tPZL

tPHZ

VX

VY

outputs

enabled

VM

tPZH

outputs

disabled

VM

outputs

enabled

001aaj913

Fig 5.

Measurement points are given in Table 9

The logic levels VOH and VOL are typical voltage output levels that occur with the output load.

Enable and disable times and 3-state propagation delays

VOH

nQn output

VOL

tt

90 %

10 %

tt

001aaj916

The logic levels VOH and VOL are typical voltage output levels that occur with the output load.

Fig 6. Transition times for nQn

1/fmax

VI

nCP input

VM

0V

tsu

tW

th

VI

nQn, nD input

VM

0V

001aae697

Fig 7.

The shading indicates where the data (nQn and nD) is permitted to change for predictable output changes.

Measurement points are given in Table 9

The logic levels VOH and VOL are typical voltage output levels that occur with the output load.

Waveforms showing minimum clock pulse width and maximum frequency and set-up and hold times for

nQn (as data input) or nD to nCP

HEF4517B_6

Product data sheet

Rev. 06 — 10 December 2009

© NXP B.V. 2009. All rights reserved.

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