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DM9102A Datasheet PDF : 77 Pages
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DM9102A
Single Chip Fast Ethernet NIC controller
Interrupt & Latency Configuration (xxxxxx3c - PCIINT)
31
24 23
16 15
MAX_LAT
Maximum Latency Timer
Minimum Grant
Interrupt Pin
Interrupt Line
MIN_GNT
INT_PIN
87
0
INT_LINE
Bit
31:24
23:16
15:8
7:0
Default
28h
14h
01h
XXh
Type
RO
RO
RO
RW
Description
Maximum Latency Timer that can be sustained (Read Only and Read As 28h)
Minimum Grant
Minimum Length of a Burst Period (Read Only and Read As 14h)
Interrupt Pin read as 01h to indicate INTA#
Interrupt Line that Is Routed to the Interrupt Controller
The value depends on mainboard.
Device Specific Configuration Register (xxxxxx40h- PCIUSR)
31 30 29 28 27 26 25 24 23
Device Specific
Link Event enable/disable
Sample Frame Event enable/disable
Magic Packet Event enable/disable
Link Event Status
Sample Frame Event Status
Magic Packet Event Status
Device Specific
Reserved
16 15
87
0
Reserved
Bit
31
30
29
28
27
26
25
24
23:16
15:8
7:0
Default
0
0
0
0
0
0
0
0
00h
00h
00h
Type
RW
RW
RW
RW
RW
RO
RO
RO
RO
RW
RO
Description
Device Specific Bit (sleep mode)
Device Specific Bit (snooze mode)
When set enable Link Status Change Wake-up Event
When set enable Sample Frame Wake-up Event
When set enable Magic Packet Wake-up Event
When set, indicates link change and Link Status Change Event occurred
When set, indicates the sample frame is received and Sample Frame Event
occurred
When set, indicates the Magic Packet is received and Magic packet Event occurred
Reserved Bits Read As 0
Device Specific
Reserved Bits Read As 0
22
Final
Version: DM9102A-DS-F03
August 28, 2000
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