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DM9102A

Single Chip Fast Ethernet NIC controller

Unspecified 

Control and Status Registers (CR)

The DM9102A implements 16 control and status registers,

which can be accessed by the host. These CRs are double

long word aligned. All CRs are set to their default values by

DM9102A

Single Chip Fast Ethernet NIC controller

hardware or software reset unless otherwise specified. All

Control and Status Registers with their definitions and offset

from IO or memory Base Address are shown below:

Register

CR0

CR1

CR2

CR3

CR4

CR5

CR6

CR7

CR8

CR9

CR10

CR11

CR12

CR13

CR14

CR15

Description

System Control Register

Transmit Descriptor Poll Demand

Receive Descriptor Poll Demand

Receive Descriptor Base Address Register

Transmit Descriptor Base Address Register

Network Status Report Register

Network Operation Mode Register

Interrupt Mask Register

Statistical Counter Register

External Management Access Register

Programming ROM Address Register

General Purpose Timer Register

PHY Status Register

Sample Frame Access Register

Sample Frame Data Register

Watchdog And Jabber Timer Register

Offset from CSR

Base Address

00H

08H

10H

18H

20H

28H

30H

38H

40H

48H

50H

58H

60H

68H

70H

78H

Default value

after reset

FEC00000

FFFFFFFF

FFFFFFFF

00000000

00000000

FC000000

02040000

FFFE0000

00000000

044097FF

Unpredictable

FFFE0000

FFFFFFXX

XXXXXX00

Unpredictable

00000000H

Key to Default

In the register description that follows, the default column

takes the form:

' <Reset Value>, <Access Type>

Where

<Reset Value>:

1

Bit set to logic one

0

Bit set to logic zero

X

No default value

<Access Type>:

RO = Read only

RW = Read/Write

RW/C = Read/Write and Clear

WO = Write only

Reserved bits are shaded and should be written with 0.

Reserved bits are undefined on read access.

Final

25

Version: DM9102A-DS-F03

August 28, 2000

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