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DM9102A Datasheet PDF : 77 Pages
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DM9102A
Single Chip Fast Ethernet NIC controller
1. System Control Register (CR0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit
24:22
21
Name
Reserved
MRM
20 Reserved
19:17 TXAP
16 Reserved
15:14 ABA
13:8
BL
7
6:2
1
26
Reserved
Reserved
Reserved
Default
0,RO
0,RW
0,RO
000,RW
0,RO
00,RW
000000,
RW
0,RO
00000
0,RO
Description
Reserved
Memory Read Multiple
When set, the DM9102A will use memory read multiple command (C/BE3~0 =
1100) when it initialize the memory read burst transaction as a master device.
When reset, it will use memory read command (C/BE3 ~ 0 = 0110) for the same
master operation.
Reserved
Transmit Automatic polling interval time
When set, the DM9102A will poll transmit descriptor automatically when it is in the
suspend state due to buffer unavailable. The polling interval time is programmable
based on the table shown below.
Bit 19
Bit 18 Bit 17
Time Interval
0
0
0
No polling
0
0
1
200us
0
1
0
800us
0
1
1
1.6ms
1
0
0
12.8us
1
0
1
25.6us
1
1
0
51.2us
1
1
1
102.4us
Reserved
Address Boundary Alignment
When set, the DM9102A will execute each burst cycles to stop at the programmed
address boundary. The address boundary can be programmed to be 8, 16, or 32
doubleword as shown below.
Bit 15 Bit 14
00
01
10
11
Alignment Boundary
Reserved
8-double word
16-double word
32-double word
Burst Length
When reset, the DM9102A’s burst length in one DMA transfer is limited by the
amount of data in the receive FIFO ( when receive ) or the amount of free space in
the transmit FIFO (when transmit ). When set, the DMA’s burst length is limited by
the programmed value. The permissible values are 0, 1, 2, 4, 8, 16, or 32
doublewords.
Reserved
Reserved
Final
Version: DM9102A-DS-F03
August 28, 2000
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