DM9000 Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.

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Lista de partido

DM9000

ISA to Ethernet MAC Controller with Integrated 10/100 PHY

Davicom Semiconductor, Inc. 

MWRH

TXPLL

TXPLH

ISR

IMR

DM9000

ISA to Ethernet MAC Controller with Integrated 10/100 PHY

Memory Data Write _ address Register High Byte

FBH

00H

TX Packet Length Low Byte Register

FCH

XXH

TX Packet Length High Byte Register

FDH

XXH

Interrupt Status Register

FEH

00H

Interrupt Mask Register

FFH

00H

Key to Default

In the register description that follows, the default column

takes the form:

<Reset Value>, <Access Type>

Where：

<Reset Value>:

1

Bit set to logic one

0

Bit set to logic zero

X

No default value

<Access Type>:

RO = Read only

RW = Read/Write

R/C = Read and Clear

RW/C1=Read/Write and Cleared by write 1

WO = Write only

Reserved bits are shaded and should be written with 0.

Reserved bits are undefined on read access.

Final

12

Version: DM9000-DS-F03

April 23, 2009

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