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DM9000 Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.

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DM9000 Datasheet PDF : 53 Pages
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
6.7 RX Status Register ( 06H )
Bit
Name
Default
7
RF
0,RO
6
MF
0,RO
5
LCS
0,RO
4
RWTO
0,RO
3
PLE
0,RO
2
AE
0,RO
1
CE
0,RO
0
FOE
0,RO
Description
Runt Frame
It is set to indicate that the size of the received frame is smaller than 64 bytes
Multicast Frame
It is set to indicate that the received frame has a multicast address
Late Collision Seen
It is set to indicate that a late collision is found during the frame reception
Receive Watchdog Time-Out
It is set to indicate that it receives more than 2048 bytes
Physical Layer Error
It is set to indicate that a physical layer error is found during the frame reception
Alignment Error
It is set to indicate that the received frame ends with a non-byte boundary
CRC Error
It is set to indicate that the received frame ends with a CRC error
FIFO Overflow Error
It is set to indicate that a FIFO overflow error happens during the frame reception
6.8 Receive Overflow Counter Register ( 07H )
Bit
Name
Default
Description
7
RXFU
0,R/C Receive Overflow Counter Overflow
This bit is set when the ROC has an overflow condition
6:0
ROC
0,R/C Receive Overflow Counter
This is a statistic counter to indicate the received packet count upon FIFO overflow
6.9 Back Pressure Threshold Register (08H)
Bit
Name
Default
Description
7:4
BPHW
3H, RW Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern
when RX SRAM free space is lower than this threshold value
Default is 3K-byte free space. Please do not exceed SRAM size
(1 unit=1K bytes)
3:0
JPT
7H, RW Jam Pattern Time. Default is 200us
bit3 bit2 bit1 bit0 time
0000
5us
0001
10us
0010
15us
0011
25us
0100
50us
0 1 0 1 100us
0 1 1 0 150us
0 1 1 1 200us
1 0 0 0 250us
1 0 0 1 300us
1 0 1 0 350us
1 0 1 1 400us
1 1 0 0 450us
1 1 0 1 500us
1 1 1 0 550us
1 1 1 1 600us
Final
15
Version: DM9000-DS-F03
April 23, 2009

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