DM9000 Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.
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DM9000 Datasheet PDF : 53 Pages
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
6.17 Multicast Address Register ( 16H~1DH )
Bit
Name
Default
7:0
MAB7
X,RW Multicast Address Byte 7
7:0
MAB6
X,RW Multicast Address Byte 6
7:0
MAB5
X,RW Multicast Address Byte 5
7:0
MAB4
X,RW Multicast Address Byte 4
7:0
MAB3
X,RW Multicast Address Byte 3
7:0
MAB2
X,RW Multicast Address Byte 2
7:0
MAB1
X,RW Multicast Address Byte 1
7:0
MAB0
X,RW Multicast Address Byte 0
(1DH)
(1CH)
(1BH)
(1AH)
(19H)
(18H)
(17H)
(16H)
Description
6.18 General purpose control Register ( 1EH )
Bit
Name
Default
Description
7:4 RESERVED 0,RO Reserved
3:0 GEP_CNTL 0001,RW General Purpose Control
Define the input/output direction of General Purpose Register
When a bit is set 1, the direction of correspondent bit of General Purpose Register
is output. GPIO0 default is output for POWER_DOWN function. Other defaults are
input
6.19 General purpose Register ( 1FH )
Bit
Name
Default
Description
7:4 RESERVED 0,RO Reserved
3:1 GEPIO3-1 0,RW General Purpose
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is reflected to pin GEPIO3-1
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit to be read is reflected from correspondent pins of GEPIO3-1
The GEPIOs are mapped to pins GEPIO3 to GEPIO1 respectively
0
GEPIO0
1,RW General Purpose
When the correspondent bit of General Purpose Control Register is 1, the value of
the bit is the output to pin GEPIO0
When the correspondent bit of General Purpose Control Register is 0, the value of
the bit to be read is reflected from pin GEPIO0. GEPIO0 default output 1 to
POWER_DOWN Internal PHY. Driver needs to clear this POWER_DOWN signal
by writing “0” when it wants PHY to be active. This default value can be
programmed by EEPROM. Please refer to the EEPROM description
6.20 TX SRAM Read Pointer Address Register (22H~23H)
Bit
Name
Default
Description
7:0 TRPAH 00H,RO TX SRAM Read Pointer Address High Byte (23H)
7:0 TRPAL 00H.RO TX SRAM Read Pointer Address Low Byte (22H)
6.21 RX SRAM Write Pointer Address Register (24H~25H)
Bit
Name
Default
Description
7:0 RWPAH 0CH,RO RX SRAM Write Pointer Address High Byte (25H)
7:0 RWPAL 04H.RO RX SRAM Write Pointer Address Low Byte (24H)
Final
18
Version: DM9000-DS-F03
April 23, 2009
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