DM9000 Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.
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DM9000 Datasheet PDF : 53 Pages
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DM9000
ISA to Ethernet MAC Controller with Integrated 10/100 PHY
6.22 Vendor ID Register (28H~29H)
Bit
Name
Default
7:0
VIDH
0AH,RO
7:0
VIDL
46H.RO
Vendor ID High Byte (29H)
Vendor ID Low Byte (28H)
Description
6.23 Product ID Register (2AH~2BH)
Bit
Name
Default
7:0
PIDH
90H,RO Product ID High Byte (2BH)
7:0
PIDL
00H.RO Product ID Low Byte (2AH)
Description
6.24 Chip Revision Register (2CH)
Bit
Name
Default
7:0
CHIPR
00H,RO
CHIP Revision
Description
6.25 Special Mode Control Register ( 2FH )
Bit
Name
Default
7
SM_EN
0,RW Special Mode Enable
6~3 RESERVED 0,RO Reserved
2
FLC
0,RW Force Late Collision
1
FB1
0,RW Force Longest Back-off time
0
FB0
0,RW Force Shortest Back-off time
Description
6.26 Memory Data Read Command without Address Increment Register (F0H)
Bit
Name
Default
Description
7:0 MRCMDX X,RO Read data from RX SRAM. After the read of this command, the read pointer of
internal SRAM is unchanged
6.27 Memory Data Read Command with Address Increment Register (F2H)
Bit
Name
Default
Description
7:0 MRCMD
X,RO Read data from RX SRAM. After the read of this command, the read pointer is
increased by 1,2, or 4, depends on the operator mode (8-bit,16-bit and 32-bit
respectively)
6.28 Memory Data Read_address Register (F4H~F5H)
Bit
Name
Default
Description
7:0 MDRAH 00H,R/W Memory Data Read_ address High Byte. It will be set to 0Ch, when IMR bit7 =1
7:0 MDRAL 00H,R/W Memory Data Read_ address Low Byte
6.29 Memory Data Write Command without Address Increment Register (F6H)
Bit
Name
Default
Description
7:0 MWCMDX X,WO Write data to TX SRAM. After the write of this command, the write pointer is
unchanged
Final
19
Version: DM9000-DS-F03
April 23, 2009
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