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A6850

Asynchronous Communications Interface Adapter

Altera Corporation 

a6850 Asynchronous Communications Interface Adapter Data Sheet

Transmitter Control

Bits 5 and 6 of the control register are the tc bits, (see Table 5). The tc bits

are responsible for:

s Enabling or disabling the interrupt caused by a transmitter data

register empty (tdre) condition.

s Controlling the request to send (nrts) signal.

s Transmitting a break character on the txdata output.

Table 5. Transmitter Control Bits

tc1

tc0

nrts

0

0

Low

0

1

Low

1

0

High

1

1

Low

Transmit

Interrupt

Disabled

Enabled

Disabled

Disabled

Break

Character

No

No

No

Yes

Receive Interrupt Enable

Bit 7 of the control register is the rie bit. When the rie bit is high, the

rdrf, ndcd, and ovr bits will assert the nirq output. When the rie bit is

low, nirq generation is disabled.

Status Register

The status register contains the status bits shown in Table 6.

Table 6. Status Register Bits

Data Bit

0

1

2

3

4

5

6

7

Bit Name

Receive data register full (rdrf)

Transmit data register empty (tdre)

Data carrier detect (ndcd)

Clear to send (ncts)

Framing error (fe)

Receiver overrun (ovr)

Parity error (pe)

Interrupt request (irq)

86

Altera Corporation

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