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A6850

Asynchronous Communications Interface Adapter

Altera Corporation 

a6850 Asynchronous Communications Interface Adapter Data Sheet

Framing Error

Bit 4 of the status register is the fe bit. The fe bit is asserted when a

received character does not end with the specified stop bit, which is

usually caused by a transmission error. The fe bit is set when the received

character is transferred to the receiver data register, and remains set until

another character is written to the receiver data register.

The fe bit is cleared when either the nreset signal is asserted, a character

is written to the receiver data register that does not have an fe error, or

the control register is set to master reset mode.

Receiver Overrun

Bit 5 of the status register is the ovr bit. The ovr bit indicates a receiver

overrun condition, i.e., one or more receiver data words have been

overwritten in the input shift register. The overrun condition is

considered to occur at the midpoint of the last received bit in the input

shift register, when the previous word (in the RDR) has not yet been read

by the microprocessor. However, the ovr bit is not set immediately when

the overrun occurs, but is set when the valid word in the RDR is read.

Thus, when the overrun condition occurs, it is the input shift register data

that is overwritten, not the RDR data.

The ovr bit is cleared when either the nreset signal is asserted, the data

in the receiver data register is read, or the control register is set to master

reset mode.

Parity Error

Bit 6 of the status register is the pe bit. When it is high, pe indicates that

the parity bit received (over the rxdata input), does not match the parity

calculated during the receive process. The pe bit is set when the data is

written into the receiver data register. If no parity is selected, the parity

error will not occur.

The pe bit is cleared when either the nreset signal is asserted, the data is

read from the receiver data register, or the control register is set in master

reset mode.

Interrupt Request

Bit 7 of the status register is the irq bit, the logical inverse of the nirq

output. See “Interrupt Operation” on page 93 of this data sheet for more

information.

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Altera Corporation

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