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A6850

Asynchronous Communications Interface Adapter

Altera Corporation 

Operation

a6850 Asynchronous Communications Interface Adapter Data Sheet

This section describes the following:

s Bus interface operation

s Receiver operation

s Transmitter operation

s Interrupt operation

s Reset operation

Bus Interface Operation

A microprocessor or other controlling device accesses the a6850 through

the bus interface, which provides a direct link to the transmit, receive,

status, and control registers.

The microprocessor interfaces with the a6850 when the cs input is set to

a logic 110 and the rnw input is set to a logic low when writing, or a logic

high when reading. The rs input then chooses the appropriate register

operation as shown in Table 7.

Table 7. Register Operations

rnw

rs

0

0

0

1

1

0

1

1

Register Operation

Control register write

Transmit data register write

Status register read

Receive data register read

When cs, rnw, and rs are set, access begins when the e input transitions

from low to high. The e input must be high for at least one txclk cycle. In

a read cycle, the data is available through the data output (do) bus on the

rising edge of the e input. In a write cycle, the data is written on the falling

edge of the e input. See Figure 3.

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