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LAN91C110

FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications

SMSC -> Microchip 

FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications

Datasheet

The CPU Data Path consists of two uni-directional FIFOs mapped at the Data Register location. These FIFOs

can be accessed in any combination of bytes, word, or doublewords. The Arbiter will indicate 'Not Ready'

whenever a cycle is initiated that cannot be satisfied by the present state of the FIFO.

4.2.3

MMU Block

The Hardware Memory Management Unit allocates memory and transmit and receive packet queues. It also

determines the value of the transmit and receive interrupts as a function of the queues. The page size is 2k,

with a maximum memory size of 128k. MIR and MCR values are interpreted in 512 byte units.

4.2.4

BIU Block

The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used for

each one. Transparent latches are added on the address path using rising nADS for latching.

With ISA, the read and write operations are controlled by the edges of nRD and nWR. ARDY is used for

notifying the system that it should extend the access cycle. The leading edge of ARDY is generated by the

leading edge of nRD or nWR while the trailing edge of ARDY is controlled by the internal LAN91C110 clock

and, therefore, asynchronous to the bus.

The BIU is implemented using the following principles:

1. Address decoding is based on the values of A15-A4 and AEN.

2. Address latching is performed by using transparent latches that are transparent when nADS=0 and

nRD=1, nWR=1 and latch on nADS rising edge.

3. Byte, word and doubleword accesses to all registers and Data Path are supported except a doubleword

write to offset Ch will only write the BANK SELECT REGISTER (offset Fh).

4. No bus byte swapping is implemented (no eight bit mode).

5. Word swapping as a function of A1 is implemented for 16 bit bus support.

6. The asynchronous interface uses nRD and nWR strobes. If necessary, ARDY is negated on the leading

edge of the strobe. The ARDY trailing edge is controlled by CLK.

4.2.5

MAC-PHY Interface Block

For the MII interface, transmit data is clocked out using the TX25 clock input, while receive data is clocked in

using RX25.

In 100 Mbps mode, the LAN91C110 provides the following interface signals to the PHY:

ƒ For transmission: TXEN100 TXD0-3 TX25

ƒ For reception: RX_DV RX_ER RXD0-3 RX25

ƒ For CSMA/CD state machines: CRS100 COL100

A transmission begins by TXEN100 going active (high), and TXD0-TXD3 having the first valid preamble

nibble. TXD0 carries the least significant bit of the nibble (that is the one that would go first out of the EPH at

100 Mbps), while TXD3 carries the most significant bit of the nibble. TXEN100 and TXD0-TXD3 are clocked

by the LAN91C110 using TX25 rising edges. TXEN100 goes inactive at the end of the packet on the last

nibble of the CRC.

During a transmission, COL100 might become active to indicate a collision. COL100 is asynchronous to the

LAN91C110’s clocks and will be synchronized internally to TX25.

SMSC LAN91C110 Rev. B

Page 12

DATASHEET

Revision 1.0 (11-04-08)

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