LAN91C110 Ver la hoja de datos (PDF) - SMSC -> Microchip

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LAN91C110

FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications

SMSC -> Microchip 

BANK 0

OFFSET

2

NAME

EPH STATUS REGISTER

TYPE

READ ONLY

SYMBOL

EPHSR

This register stores the status of the last transmitted frame. This register value, upon individual transmit packet

completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt processing should use

the copy in memory as the register itself will be updated by subsequent packet transmissions. The register can be used

for real time values (like TXENA and LINK OK). If TXENA is cleared the register holds the last packet completion status.

HIGH

BYTE

LOW

BYTE

Reserved

0

TX

DEFR

0

LINK_

OK

-nLNK

pin

LTX

BRD

0

Reserved

0

CTR

_ROL

0

SQET

0

16COL

0

EXC

_DEF

0

LTX

MULT

0

Reserved LATCOL Reserved

0

0

0

MUL

COL

0

SNGL

COL

0

TX_SUC

0

LINK_OK - General purpose input port driven by nLNK pin inverted. Typically used for Link Test. A transition on the value

of this bit generates an interrupt.

CTR_ROL - Counter Roll Over. When set one or more 4 bit counters have reached maximum count (15). Cleared by

reading the ECR register.

EXC_DEF - Excessive Deferral. When set last/ current transmit was deferred for more than 1518 * 2 byte times. Cleared

at the end of every packet sent.

LATCOL - Late collision detected on last transmit frame. If set a late collision was detected (later than 64 byte times into

the frame). When detected the transmitter jams and turns itself off clearing the TXENA bit in TCR. Cleared by setting

TXENA in TCR.

TX_DEFR - Transmit Deferred. When set, carrier was detected during the first 6.4 μs of the inter frame gap. Cleared at

the end of every packet sent.

LTX_BRD - Last transmit frame was a broadcast. Set if frame was broadcast. Cleared at the start of every transmit

frame.

SQET - Signal Quality Error Test. SQET bit is always set after first transmit, except if SWFDUP=1. As a consequence,

the STP_SQET bit in the TCR register cannot be set as it will always result in transmit fatal error. Transmission stops and

EPH INT is set if STP_SQET is in the TCR is also set when SQET is set. This bit is cleared by setting TXENA high.

16COL - 16 collisions reached. Set when 16 collisions are detected for a transmit frame. TXENA bit in TCR is reset.

Cleared when TXENA is set high.

LTX_MULT - Last transmit frame was a multicast. Set if frame was a multicast. Cleared at the start of every transmit

frame.

MULCOL - Multiple collision detected for the last transmit frame. Set when more than one collision was experienced.

Cleared when TX_SUC is high at the end of the packet being sent.

SMSC LAN91C110 Rev. B

Page 20

DATASHEET

Revision 1.0 (11-04-08)

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