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CB55000

HCMOS7 Standard Cells

STMicroelectronics 

CB55000 Series

4 DESIGN FOR TESTABILITY

The test time and cost for ASIC testing increases exponentially as the complexity and size of the ASIC grows.

Using a design-for-testability methodology allows large, more complex ASICs to be efficiently and economically

tested.

At system level, STMicroelectronics fully supports IEEE 1149.1; the I/O structure utilized in this family is com-

pletely compatible. Several types of core scan cells are provided in the CB55000 Series library. Examples in-

clude FDxS/FJKxS edge sensitive and LDxS level sensitive cells. Non-overlapping clock generator macros are

also available.

Test coverage and reliability are further supported by IDDQ (quiescent current) testing; all blocks are designed

to be “IDDQable” so that anomalous leakage due to metal bridging and dielectric defects can be screened using

proper set of vectors extracted from the test patterns.

For parametric and lddq testing, the I/O cells contain a dedicated test interface as described previously (see I/

O Test Interface’ on page 7).

5 EVALUATION DEVICE

As per STMicroelectronics’ standard policy, all cells and macro-blocks are fully validated and characterized on

silicon through dedicated test vehicules, before final release in the library. In addition, a 3 million-gates evalua-

tion chip: CB55Q, has been designed and in order to demonstrate the performances and qualify the global

CB55000 library, as well as verify the effectiveness of the design system.

CB55Q is packaged in a 256 Ball Grid Array (BGA) and permits accurate characterisation of most representative

cells from the library including I/O buffers, single and mixed cell chains (IV, ND2, NR2...),Flip-flops and memory

cuts from various generators.

Typical result on ring SSI chain in ring oscillator mode show a mean between Thl and Tlh of around 37 ps for

an inverter with 1 standard load , and toggle frequency of above 1 GigaHertz for an FD2.

Figure 5. CB55Q Die View

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