CB55000 Ver la hoja de datos (PDF) - STMicroelectronics
Número de pieza
componentes Descripción
Lista de partido
CB55000 Datasheet PDF : 15 Pages
| |||
CB55000 Series
3.4 I/O Test Interface
The I/O cells have a dedicated test interface to facilitate parametric and lddq testing of devices. This test interface
connects standard core signals or dedicated test signals to the I/O cells allowing all output buffers to be driven high,
low or put into tri-state regardless of the state of the internal logic.
This greatly simplifies parametric testing of the device and also assisting customers who wish to use this feature
during board testing. Note that all output buffers can be tri-stated by this function including buffers that normally
do not tri-state.
This test function also turns off all pull down resistors, shuts down all differential receivers and converts them
into standard CMOS receivers. This allows lddq test methodologies to be employed in a very efficient way,
avoiding unneeded circuit overhead.
3.5 Macrocells
The CB55000 series has internal macrocells that are robust in variety and performance. The cell selection has
been driven by the need of Synthesis and HDL-based design techniques. This offering is rich in buffers, complex
combination cells and multi-power drive cells, which allow the Synthesis tool to create a netlist compatible with
the requirements of Place and Route tools.
Macrofunctions are a series of soft-macros facilitating quick capture of large functional blocks and are available
for such functions as counters, shift registers and adders. Macrofunctions are implemented at layout by utilizing
macrocells and interconnecting to create the logic function.
3.5.1 Module generators
A series of module generators using compiled cell generation techniques are available to support a range of
megacells. These modules enable the designer to choose individual parameters in order to create a compiled
cell, which meets the specific application requirements. These include ROM, single and dual port RAM, multi-
port RAM and FIFO.
For most of the above memories, two different generators are provided, one optimized for speed and one opti-
mized for power. All memories have a complete standby mode where current consumption is limited to process
leakage.
Table 3. List of module generators
Generator
Description
Romd
Rom3
SPS2
SPS3
SPS4
SPS5
SPS6
High speed Sync.
Diffusion ROM
Low power Sync.
Diffusion ROM
High speed Sync.
Single port RAM
Low power Sync.
Single Port RAM
Small cuts Sync.
Low power
Single Port Ram
Low power Sync.
Single Port RAM
High density
Low power & voltage
High density Sync.
Single Port Ram
Bit (Min.)
128
128
64
16
2
1000
2000
Kbit (Max)
2000
256
512
32
16
512
2000
byte write
supported
Word width
(Max.)
64
32
64
32
128
64
32
7/15
Share Link: 