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CB55000

HCMOS7 Standard Cells

STMicroelectronics 

CB55000 Series

1 GENERAL DESCRIPTION

The CB55000 standard cell series uses a high performance, low-voltage, 0.25 µm drawn (0.20 µm effective),

six metal levels CMOS process HCMOS7 to a 90 pico-second internal delay while offering very low power dis-

sipation and high noise immunity.

With an average routed gate density of 30,000 gates/mm2, the CB55000 family allows the integration of up to

15 million equivalent gates and is ideal for high-complexity or high-performance devices for computer, telecom-

munication and consumer products.

With a typical gate delay of 70 ps (for a 2-input NAND gate at fan-out 1), the library meets the most demanding

speed requirements in telecommunication and computer application designs today.

Optimized for 2.5 V operation, the library features a power consumption of less than 70 nW/Gate/MHz (fan-

out=1) and 30 nW/Gate/MHz (fan-out=1) at 1.8 V.

The I/O buffers can be fully configured for both 2.5 V and 3.3 V interface options, with several high speed buffer

types available. These include: low voltage differential (LVDS) I/Os, PCI/AGP, PECLs, and HSTL.

The pad pitch down to 50 µm, in a staggered arrangement, meets the requirements of high pin-count devices

which tend to become pad-limited at such library densities. For very high pin-count ICs, advanced packaging

solutions such as Chip Scale Packaging in fine pitch BGA are available.

New packaging solutions using a flip-chip approach are currently being developed.

Figure 2. HCMOS7 Front end cross section

MOS gate length: 0.25 µm, Shallow Trench Isolation, M1: Tungsten

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