GENERAL DESCRIPTION
The CB55000 standard cell series uses a high performance, low-voltage, 0.25 µm drawn (0.20 µm effective), six metal levels CMOS process HCMOS7 to a 90 pico-second internal delay while offering very low power dissipation and high noise immunity.
With an average routed gate density of 30,000 gates/mm2, the CB55000 family allows the integration of up to 15 million equivalent gates and is ideal for high-complexity or high-performance devices for computer, telecommunication and consumer products.

FEATURE
■ 0.25 micron drawn (0.20 micron effective channel length process), six layers of metal connected by fully stackable vias and contacts, Shallow Trench Isolation, low resistance, salicided active areas and gates. Deep UV lithography.
■ 2.5 V optimized transistor with 3.3 V I/O and supply interface capability.
■ Average gate density: 30 K/mm2, plus low power consumption of 70 nanoWatt/Gate/MHz/ Stdload.
■ Two input NAND delay of 90 pS (typical) with fanout=2.
■ Library available in commercial, industrial and military temperature range with supply ranging from 2.70 V down to 1.8 V for the core according to EIA/JESD 8-5 specification. Additional low voltage range down to 1.5 V for very low voltage/low power applications supported
■ Broad I/O functionality including: – Low Voltage CMOS. – Low Voltage TTL, PECL, HSTL, SSTL, LVDS, PCI.
■ AGP 2X and 4X, USB to support 2.5 V and 3.3 V I/O interface according to EIA/JESD 8A specification.
■ Drive capability up to 8 mA per buffer with slew rate control, current spike suppression impedance matching, and process compensation capability to reduce delay variation.
■ Designs easily portable from previous generations of CB45000 through cell mapping with an average factor 2 density increase, 1.7 speed increase and 2.5 power reduction at respective nominal voltages.
■ Generators to support Single Port, Dual port and multiple Port RAM, and ROMs with BIST options.
■ Extensive embedded function library including ST DSP and micro-cores, third-party IPs, Synopsys and Mentor Inventra synthetic libraries ideally suited for complete System On Chip fast integration .
■ 80 µm pitch linear and 50 µm staggered pad libraries.
■ Fully independent power and ground configuration for core and I/Os supported.
■ I/O ring capability up to 1500 pads.
■ Latch-up trigger current > +/- 500 mA. ESD protection above 4 kV in H.B.M.
■ Oscillators and PLLs for wide frequency spectrum.
■ Broad range of more than 600 SSI cells.
■ Design for test features including IEEE 1149.1 JTAG Boundary Scan architecture.
■ Synopsys, Cadence and Mentor based design systems with interface from multiple workstations.
■ Broad range of packaging solutions, including BGA, LBGA, TQFP, PQFP, PLCC up to 1000 pins with enhanced power dissipation options.
■ 1.25 GigaHertzGigabit DLL technique.